The present invention relates to an information processing apparatus, an information processing method, and a program. More particularly, the invention relates to an information processing apparatus, an information processing method, and a program for controlling the amount of power consumed by an information processing apparatus to an actually required level in a manner permitting easy standardization of techniques for such power management and enabling simple transport of the techniques from one apparatus to another without running the risk of quality defects.
Recent years have witnessed a dramatic increase in CPU (central processing unit) capabilities. The upsurge in performance has been accompanied by the proportionately boosted maximum consumption of power by the CPUs.
In practice, however, there are few occasions on which the CPU runs in an operating state requiring maximum power dissipation. In most cases (i.e., in normal operating state), the latest CPUs consume approximately the same level of power as their predecessors.
Under these circumstances, it has become more difficult than ever to design a power supplying apparatus (also called the power supply unit hereunder) for powering information processing apparatuses each carrying one of such high-performance CPUs.
To design a typical power supply unit requires taking into consideration the maximum power consumption of an apparatus coupled with the power supply unit. More specifically, the power supply unit is designed to deal with the putative case where the CPU incorporated in an information processing apparatus, on-board chips, internal drives, and any devices connected to external device connectors of the apparatus operate all at once at their maximum capacity.
Taking the estimated maximum power dissipation requirement into account in its design, the power supply unit tends to be large-sized and costly when implemented.
Obviously, the bulky, expensive power supply unit is not suited for use on board a portable information processing apparatus such as a mobile computer or a notebook-size personal computer (hereunder, referred to simply as the notebook PC as needed).
As mentioned above, there are few occasions on which the CPU is made to run at capacity consuming the maximum level of power. That means the power supply unit designed simply to address maximum power dissipation tends to be redundant in its performance.
On the other hand, if the power supply unit is designed merely to deal with a steady level of power consumption by the CPU in its normal operating state without regard to the possible maximum level of power consumption, then the unit is subject to an excess supply of power when the CPU runs close to its capacity.
In the face of such an excess supply of power, the power supply unit stops its feed of power to prevent quality defects. In that case, the information processing apparatus utilizing the power supply unit is abruptly deprived of power and becomes incapable of remaining consistent in its processing. In other words, data losses can occur.
It follows that devising a better power supply unit is not enough; it is also necessary to come up with techniques for reducing the level of power consumption by the information processing apparatus itself. Some of such techniques have been proposed in the past. For example, Japanese Patent Laid-open No. 2000-172387 (called the Reference 1 hereunder) discloses a method for switching operation modes of the CPU to reduce power consumption of an information processing apparatus whenever the maximum power consumption level of the apparatus is predicted to exceed a predetermined threshold value.
According to the method disclosed by the Reference 1, the maximum power consumption of the information processing apparatus is a value calculated predictively on the basis of a base load and CPU operation status specific to the apparatus in question. As one disadvantage of the method, the base load and the CPU type vary from one model of information processing apparatus to another, so that a dedicated set of predictive techniques is needed for each model. That means it takes time and effort to transport the techniques for power consumption control between different models of information processing apparatuses. This amounts to a considerable difficulty in standardizing the techniques.
According to the method of the Reference 1, it is necessary to effect power management in keeping with very large values of power limit so that quality defects will not occur even under the most rigorous conditions. This results in a power management scheme subject to a far severer amount of power limit than is actually needed. As another disadvantage of the method, the proposed power management scheme leads to an acute degradation in performance of the information processing apparatus under power limit control.
Furthermore, with the method of the Reference 1 in use, it takes time to switch operation modes of the CPU for power management (for example, it takes a delay time of two seconds for Intel Corporation's throttling mode actually to come into effect following a designated switchover to that mode). As a further disadvantage of the disclosed method, the delay time can hamper the effort to limit power consumption to a managed level in time. That means there is a possibility of quality defects taking place.